There are two general classes of communication buses used in microprocessor systems. The first class comprises the “main” system bus, which is usually a parallel arrangement of address and data signals. Such a parallel bus is typically used to communicate with “high speed” peripheral or memory devices. An example of such a set of signals is the Peripheral Component Interconnect (PCI) bus.
A second class of microprocessor communication buses may be called serial buses. Serial buses are frequently employed in many types of computer systems, for example hand held computers. A serial bus may enable, for example, a system processor to communicate with an analog to digital converter which measures battery voltage.
Several standard serial buses have been designed and are widely implemented on both standard and custom integrated circuits. The standardization of a bus design allows products from a wide range of manufacturers to work together, beneficially reducing the workload of product design engineers. One exemplary standard serial bus is known as the Serial Peripheral Interconnect bus, or SPI bus, commercially available on integrated circuit products from Motorola Incorporated, as well as other manufacturers. Another well known standard interconnect bus is known as the Inter-Integrated Circuit bus, commercially available on integrated circuit products from Philips, as well as other manufacturers. The Inter-integrated Circuit bus is more generally known as the I2C (read “I-squared C”) bus, and is frequently printed without the superscript as “I2C.”
In general, on a serial bus, e.g., the I2C bus, one device will control a communication at a time. Such a controlling device is known as a master device, and is said to “master” the bus. Other types of devices may be known as slave devices. Slave devices are more passive than master devices. For example, a slave device may only communicate in response to a communication initiated by a master device.
The I2C bus comprises two signal lines, a serial clock line and a serial data line. In order to initiate a communication with a slave device, a master will drive the clock line and synchronously send out a multi-bit address on the data line. Slave devices on the bus respond to specific addresses. When a slave detects its specific address, the slave device initiates its specific function. A slave may be a receive-only device, or it may respond to an inquiry from a master device. In all cases, however, a master device provides and drives the clock signal used to synchronize the data line.
The I2C bus, as well as other serial buses, allows multiple masters to share control or “mastership” of the bus. In general, multiple master devices take turns controlling or “mastering” the bus. In the case of the I2C bus, the I2C standard specifies an arbitration process to determine which master will gain control of the bus. Unfortunately, implementation of the arbitration function and other support for multiple master devices requires additional design effort, additional design duration and additional product cost. As an unfortunate consequence, some otherwise attractive bus master devices have been designed without support for multiple bus masters. Deleteriously, new functional requirements, e.g., product upgrades, that require an additional bus master device, may not be added to a bus comprising a master device that does not support additional bus master devices.
It is expensive in terms of time, personnel resources and monetary outlays to design an integrated circuit. Designs typically require long periods of development, extensive qualification testing and significant non-recurring engineering expenses, e.g., for integrated circuit mask fabrication. A manufacturer may have additional costs associated with managing existing inventory made obsolete or less valuable by a design change to an existing product. Consequently, any addition of function(s) to a serial bus should be compatible with existing bus implementations without the need for revamping well established designs and products.
Thus a need exists for a method and system to add a master controller to a serial bus supporting a single master only. A further need exists to meet the previously identified need that is complimentary and compatible with conventional computer system design techniques. In conjunction with the aforementioned needs, a still further need exists for adding a master to a pre-existing design without revamping established integrated circuit elements.